Mr. Hemant Mallapur
Co-founder & Exec. VP Engineering, Saankhya Labs
Keynote Title : Software Defined Radio – VLSI architecture for Wireless Communications
India-based deep-tech entrepreneur with 3 decades of R&D in wireless semiconductor technologies with 5 key patents in Software Defined Radio systems. Co-founder & Executive VP of Engineering of Saankhya Labs – India’s 1st Fabless Semiconductor company. Raised investment from Intel, General Motors & Sinclair and expanded into an OEM supplier for 5G, Broadcast, Satcom, Defense equipment with customers in US & India. Saankhya grew into an MSME over 15 years with a headcount of 400. Saankhya has been recently acquired by Tata Group company Tejas Networks. Saankhya’s 5G products were demonstrated to the Honorable PM Shri Narendra Modiji at India Mobile Congress & it is recognized as a leader in India’s Atmanirbhar mission in 5G. Saankhya won many international awards including IMS Research Semiconductor TV Innovation, FT Asia Pacific High Growth companies & CII Industrial Innovation. Hemant was featured in EDN Asia magazine as a Tech Innovator and was part of Sage Inc, a US-based company that had a successful IPO on NASDAQ. He obtained his B.Tech in Electronics and Communications Engineering from College of Engineering, Jawarahlal Technological University, Hyderabad in 1992. He lives in Bangalore with his wife Jasmina and daughter Diya.
Inauguration Keynote Speaker
Dr. Parthasarathy Ramaswamy
Senior Principal Engineer at Intel Corporation
Keynote Title: DDR Memory overview
Dr. Partha Ramaswamy is a senior principal engineer in the data center group at Intel corporation. His expertise spans across client and data center compute platform electricals. His research interests include advanced materials for high speed interconnect solutions.
Keynote Speaker 1
Mr. Prasanna Thyamagondlu
Director- Product Development, Capgemini
Keynote Speaker 2
Dr. Vaibhav Pratap Singh
Principal Technical Officer, CDAC
Keynote Title : DIR-V ecosystem in India
Mr. Vaibhav Pratap Singh joined C-DAC in 2014 and is currently working as Principal Technical Officer with the IoT team. He is also currently pursuing his Ph.D at IIT Madras. He has done MS (by Research) from IIT Madras and B.Tech in ECE from DIT Dehradun. His current interest includes Quantum Key Distribution, Machine learning, Electronics for Quantum Computing and Communications. His projects, over the years, have been majorly in the domain of Embedded Systems and Internet of Things. He has been awarded in past as Bayer Young Environmental Envoy by Bayer India and United Nations Environment Program (UNEP) for designing a Wireless Sensor Network to do soil CO2 monitoring. He has filed 3 patents and has multiple journal and conference publications.
Dr. N. S. Murthy
Consultant to LeCo Consulting
Tutorial Title: VLSI Fab and Test Demystified
Dr. N.S. Murthy is currently a consultant to LeCo Consulting. Till Jun 2020, he was the chairman and professor of the department of Electronics and Communication Engineering of Amrita Vishwa Vidyapeetham, Bengaluru. Till May 2012, he was the Director of New Business Initiatives and Academic Relations of NXP Semiconductors, Bangalore. Before this, Dr. Murthy was the Director, Technology Management and Academic Relations and General Manager of the Reuse Technology Group of Philips Semiconductors. Till Nov 2000, Dr. Murthy served IBM as Deputy General Manager of Hardware design Group and prior to that he was with Semiconductor Complex Limited in various roles. Dr. Murthy obtained Ph.D. in Microelectronics from the Department of Electrical Engineering of IIT Bombay, MBA from IGNOU, Delhi and Mastering the Semiconductor Business (mini-MBA) from Ashridge Management College, London. He has 29 years of industrial experience and 8 years of academic experience. He has two granted US/European patents and 50+ Scopus indexed publications/presentations in international journals/conferences. Dr. Murthy’s interests span to VLSI and embedded systems design and fabrication.
This tutorial “VLSI fab, assembly and test demystified” will cover the basics of the technologies and processes applied in the fabrication, assembly and test of VLSI circuits. This will enable the participants to get an idea of the multidisciplinary nature of the whole post VLSI design technologies and the complexities involved. The aim is to help the VLSI designers and those involved in semiconductors in general to appreciate the major and the most complex side of the semiconductors business, i.e. the post design tape out phase. Physical samples or mask plates, silocon wafers and devices in different stages or manufacturing process will be shown.
Mr. Sharan A.
Workshop Title: System Design Flow using Xilinx Vivado and Vitis on Pynq-Z2 Board
Mr. Sharan A is the Application Engineer for Xilinx & Mentor products at CoreEL Technologies, Bengaluru. He holds a B.E degree from Sri Krishna College Of Engineering and Technology Coimbatore. He has 2 years of extensive experience in Technical Education. He is currently providing technical engagement and solutions to educational institutions as a part of CoreEl University Program. He has technical hands-on expertise in Xilinx & MentorGraphics. His area of interests are RTL,Embedded-C,ASIC design.
This workshop “System Design Flow using Xilinx Vivado and Vitis on Pynq Z2 Board” will cover the digital design implementation using Vivado design suit. This will enable the participants to get an idea of Vivado design flow. In addition, this workshop will cover the Pynq Python framework flow for AI-ML application. This will enable the participants to get an idea of AI-ML application implementation using Pynq board. Further, this workshop will cove the Pynq Python framework flow for image processing. This will enable the participants to get an idea of image processing implementation using Pynq board.